Data and clock signal recovery operations are typically employed in asynchronous transceiver systems. Typically, the receiver timing reference, that is, the clock recovery, in such systems is derived from the incoming or received data pulses and the received data pulses are then retimed to be aligned or synchronous with this derived receiver timing reference. Clock recovery may be implemented, for example, by using an analog phase-locked loop (PLL) or a digital data and clock recovery circuit employing an oversampling clock, referred to as XCLK in this context. The term oversampling clock refers to a reference clock having a clock rate or sampling rate faster than the nominal carrier frequency of the signal to be received. Such digital data and clock recovery circuits are sometimes preferred over analog PLLs for a variety of reasons. For example, voltage or current controlled oscillator (VCO/ICO) trimming may not be required, timing recovery may be substantially immune from false-lock, and substantially immune from silicon processing, temperature, and power supply variations, to recite only a few reasons. Furthermore, the architecture for such digital data and clock recovery circuits may be relatively easy to manufacture and test in comparison with analog PLLs.
Unfortunately, phase quantization error or generated jitter for such a digital data and clock recovery circuit may be significant in asynchronous transceivers. Typically, the less the phase quantization error, the better is the timing recovery that is achieved. It is well-known that the phase quantization error due to oversampling is generally inversely proportional to the oversampling ratio. The oversampling ratio is defined, in this context, as the ratio of the XCLK clock pulse frequency, or oversampling clock frequency, to the input or received signal carrier frequency. Thus, by increasing the oversampling frequency, the phase quantization error may be reduced. However, high frequency reference clock sources are difficult to design, and, furthermore, may consume significant amounts of power relative to the power supply, especially in a low-voltage environment. A need therefore exists for a method or technique of reducing the phase quantization error of a digital clock and data timing recovery system other than by simply increasing the oversampling frequency.